Compaq AlphaServer ES40 Manuel d'utilisateur Page 6

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4
Architecture
This system is designed to maximize the potential of the Alpha
21264 chip. The traditional bus interconnect has been replaced
by a switch-based interconnect system. With a bus design, the
processors, memory, and I/O modules share the bus. As the
number of bus users increases, the transactions interfere with
one another, increasing latency and decreasing aggregate
bandwidth. However, with a switch-based system there is no
degradation in performance as the number of CPUs, memory,
and I/O users increase. Although the users increase, the speed
is maintained.
With a switch-based, or point-to-point interconnect, the
performance remains constant, even though the number of
transactions multiplies. The switched system interconnect uses
a set of complex chips that route the traffic over multiple
paths. The chipset consists of one C-chip, two P-chips, and
eight D-chips.
C-chip. Provides the command interface from the CPUs
and main memory. Although there is only one C-chip in
the system, it allows each CPU to do transactions
simultaneously.
D-chips. Provide the data path for the CPUs, main
memory, and I/O.
P-chips. Provide the interface to two independent 64-bit
33 MHz PCI buses.
This chipset is similar to that used in the AlphaServer DS20
system; however, this chipset supports up to four CPUs and up
to 32 Gbytes memory (16 GB available now). Interleaving
occurs when at least two memory arrays are used.
Two 256-bit memory buses support four memory arrays,
yielding a 5.2 Gbytes/sec system bandwidth. Transactions are
ECC protected. Upon the receipt of data, the receiver checks
for data integrity and corrects any errors.
System Block Diagram
C-chip
First
CPU
8 D-chips
P-chip
P-chip
1 or 2
Memory
Arrays
Memory
Arrays
64 bit PCI
64 bit PCI
Command, Address, and Control lines for each Memory Array
Control lines for D-chips
Memory
Data
Bus
CPU
Data
Bus
CAPbus
PAD
Bus
PKW
1400A-99
1 or 2
CPUs
B-cache
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