6
Processor Module
An AlphaServer ES40 can have up to four CPU modules.
In addition to the Alpha 21264 chip, the CPU module has a
4-Mbyte second-level cache and a 2.2V DC-to-DC converter
with heatsink that provides the required voltage to the Alpha
chip. Power-up diagnostics are stored in a flash ROM on the
module.
PK0271
Processor Configuration Rules
•
The first CPU module is installed in CPU slot 0.
•
Additional CPUs are installed in the next available slot.
•
CPUs must be identical in speed and cache size.
Memory
Memory throughput in this system is maximized by the
following features:
•
Two 256-bit wide memory data buses
•
Very low memory latency (120 ns) and high bandwidth
with 12 ns clock
•
ECC memory
The switch interconnect can move a large amount of data over
two independent memory data buses. Each data bus is 256 bits
wide (32 bytes). The memory bus speed is 83 MHz. This
yields 2.67 GB/sec bandwidth per bus (32 x 83 MHz = 2.67
GB/sec). The maximum bandwidth is 5.2 GB/sec (2.67 x 2).
The design challenge was to maximize the capabilities of the
two wide data buses. Distributing the 256 data bits equally
over two memory motherboards (MMBs) was one solution:
simultaneously, in a read operation, 128 bits come from one
MMB and the other 128 bits come from another MMB, to
make one 256-bit read. Another 256-bit read operation can
occur at the same time on the other independent data bus.
In addition, two address buses per MMB (one for each array)
allow overlapping/pipelined accesses to maximize use of each
data bus. When all arrays are identical (same size and speed),
the memory is interleaved; that is, sequential blocks of mem-
ory are distributed across all four arrays.
256 Data + 32 Check Bits
Data
Bus 0
MMB2 MMB0 MMB3 MMB1
256 Data + 32 Check Bits
Address Arrays 2 & 3
Address Arrays 0 & 1
Data
Bus 1
C-Chip
To all eight D-ChipsTo all eight D-Chips
PK0272
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